To enhance performance and reduce power consumption of semiconductor integrated devices, the three-dimensional stacking of transistors has been used since it is effective in reducing the parasitic capacitance and the parasitic resistance caused by short wiring. As technology for providing the three-dimensional stacking, the technology for stacking Si chips and connecting them by Through Silicon Vias (TSV) is under development. However, since the TSV size is greater than the wiring intervals of an ordinary CMOS process by at least two orders of magnitude, there is a limit to how much the wiring density can be increased for the purpose of enhancing wiring efficiency. In addition, since the area penalty for the TSV is large and is not negligible, the design of circuits may be affected and the manufacturing cost may increase. For this reason, there is a demand for technology for enabling wiring connection to be performed at higher density.
As a method for solving the area penalty problem of the TSV, there is a proposal wherein SOI substrates are pasted and stacked in three dimensions. According to this proposal, the performance of an upper transistor is almost the same as that of a base CMOS. (See P. Batude et al., VLSI Technical Digest, (2011) p. 158 (a)nd P. Batude et al., IEDM Technical Digest, (2011) p. 151). However, this proposal has some problems to be solved, such as high manufacturing cost due to the pasting of crystalline Si layers, and the adverse effects which the process temperature of upper layer transistors (which is as high as 600° C.) may have on the ground CMOS.
It is proposed to provide an a-Si-TFT CMOS between intermediate wiring layers of a CMOS or on top of the wiring layers of a CMOS. (See T. Naito et al., 2010 Symposium on VLSI Technology, Technical Digest Papers, p. 219). However, the performance of the a-Si-TFT is markedly inferior to that of an ordinary type of Si-SMOS, and it is hard to determine a proper threshold. For this reason, the driving voltage is inevitably high, or the leak current is high. Despite the three-dimensional stacking, however, the performance is not very enhanced, and the consumption power is not reduced sufficiently.